For additional information or questions, please email и продолжить All documents and Visual Analog and SPI Controller are available at the High Speed ADC Evaluation Boards page. The AD9653 data sheet provides additional information related to device configuration and performance, and should be consulted when using these tools. User guide UG-328 provides documentation and instructions to configure the device for performance evaluation in the lab.

The SPI Controller software package is also compatible with this hardware, and allows the user to access the SPI programmable features of the AD9653. The Visual Analog software package, which is used to interface with the device's hardware, allows users to download captured data for analysis with a user-friendly graphical interface. It is designed to interface directly with the HSC-ADC-EVALC data capture card, allowing users to download captured data for analysis. This reference design provides all of the support circuitry required to operate the devices in their various modes and configurations. The AD9653-125EBZ is an evaluation board for the AD9653, quad 16-bit ADC. The SPI control offers a wide range of flexible features to meet specific system requirements

A data clock output (DCO) operates at frequencies of up to 500 MHz and supports double data rate (DDR) operation. Pin compatible to the AD9253 14-bit quad and AD9633 12-bit quad ADC.Low power of 163 mW/channel at 125 MSPS with scalable power options.Four ADCs are contained in a small, space-saving package. It is specified over the industrial temperature range of −40☌ to

The AD9653 is available in a RoHS-compliant, 48-lead LFCSP. With custom user-defined test patterns entered via the serial port Include built-in deterministic and pseudorandom patterns, along The ADC contains several featuresĭesigned to maximize flexibility and minimize system cost, such as programmable output clock and data alignment and digital Power-down is supported and typically consumes less than 2 mW A data clock output (DCO) forĬapturing data on the output and a frame clock output (FCO)įor signaling a new output byte are provided. The ADC automatically multiplies the sample rate clock for theĪppropriate LVDS serial data rate.

Serial analog to digital converter